Semiconductor Dynamic Random Access Memory (DRAM) devices have been applied in the integrated circuits for many years. A memory cell typically consists of a storage capacitor and an access transistor for each bit to be stored by the semiconductor DRAM. Either the source or drain of the transistor is connected to one terminal of the capacitor. The other side of the transistor and the transistor gate electrode are connected to external connection lines called a bit line and a word line, respectively. The other terminal of the capacitor is connected to a reference voltage. Thus, the formation of a DRAM memory cell comprises the formation of a transistor, a capacitor and contacts to external circuits.
With the coming of Ultra Large Scale Integrated (ULSI)DRAM devices, the sizes of memory cells have gotten smaller and smaller such that the area available for a single memory cell has become very small. This has caused a reduction in capacitor area, which in turn results in a reduction in cell capacitance. The reduction in memory cell area is required for high density DRAMs. This causes reduction in capacitor area, resulting in the reduction of cell capacitance. For very small memory cells, planar capacitors become very difficult to use reliably. Specifically, as the size of the capacitor decreases, the capacitance of the capacitor also decreases. Similarly, the amount of the charge capable of being stored by the capacitor decreases. This results in the capacitor being very susceptible to .alpha. particle radiation. Additionally, as the capacitance decreases, the charge held by storage capacitor must be refreshed often. A simple stacked capacitor can not provide sufficient capacitance, even with high dielectric films, such as Ta.sub.2 O.sub.5, for the DRAM capacitor.
Prior art approaches to overcome these problems have resulted in the development of the various types of capacitors. Such as the trench capacitor (see for example U.S. Pat. No. 5,374,580) and the stacked capacitor (see for example U.S. Pat. No. 5,021,357). However, the trench capacitor has the well-known problem of "gated diode leakage," which is the leakage of current resulting in the trench capacitor failing to hold a charge. The manufacture of the stacked capacitor causes difficulties due to the limitation of the lithography technique. In addition, reducing the thickness of the dielectric also can improve the capacitance of the capacitor, but this approach is limited because of yield and reliability problems.
A capacitor-over-bit-line (COB) cell with a hemispherical-grain (HSG) polysilicon storage node has been developed (please see "A CAPACITOR-OVER-BIT-LINE CELL WITH HEMISPHERICAL-GRAIN STORAGE NODE FOR 64 Mb DRAMs", M. Sakao etc. microelectronics research laboratories, NEC Corporation). The HSG-Si is deposited by low pressure chemical vapor deposition method at the transition temperature from amorphous-Si to polycrystalline-Si. Further, a cylindrical capacitor using Hemispherical-Grained Si has been proposed (see "A NEW CYLIDRICAL CAPACITOR USING HEMISPHERICAL GRAINED Si FOR 256 Mb DRAMs", H. Watanabe et al., Tech Dig,Dec. 1992, pp.259-262).